The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a multi-level staked structure of plural staked semiconductor bear chips such as IC or LSI, wherein the plural staked semiconductor bear chips have the same external electrode patterns as each other.
A dual line memory module (DIMM) structure has been used for mounting a plurality of semiconductor packages. FIG. 1 is a schematic perspective view illustrative of a dual line memory module (DIMM) structure for mounting a plurality of semiconductor packages. In accordance with the dual line memory module (DIMM) structure, plural semiconductor packages 101 such as TSOPs (thin small outline packages) and CSPs are packaged in parallel on both top and bottom surfaces of a dual line memory module substrate 100. In order to reduce the packaging area, it is effective that each of the semiconductor packages 101 has a multilevel stacked structure of plural semiconductor packages stacked.
If each of the semiconductor packages 101 has a multilevel stacked structure of plural semiconductor packages stacked, a multilevel interconnection layout is necessary. To make this multilevel interconnection layout, it is further necessary that the multilevel stacked semiconductor packages are different from each other in interconnection layout of address lines and data lines, whereby the bottom level semiconductor package are likely to have increased numbers of through holes and external terminals. This means that the design or layout of the stacked semiconductor chips varies depending upon the number of the levels of the stacked semiconductor chips. The multilevel stacked structure makes it inefficient to conduct the design and manufacturing.
It has been proposed that in order to realize the efficient design and manufacturing, selectable signal lines or chip select signal lines are used throughout the multilevel for making the address lines and data lines common on the individual levels for unification to the electrode patterns and interconnection patterns and to the number of the signal lines throughout the multilevels. One example of the stacked modules of this type is disclosed in Japanese patent no. 2870530. FIG. 2 is a schematic perspective view illustrative of a conventional stacked module of plural memory bear chips mounted on interposers stacked in multilevels. Plural memory bear chips 105 are mounted on interposers 106. The interposers 106 are stacked in the form of multilevels. The stacked interposers 106 are electrically connected to each other through solder balls 107.
Each of the interposers 106 is provided with chip select signal lines for selecting a level, on which the memory bear chip should execute a read or write commend. The chip select signal lines are laid out so that the address lines and data lines of the memory bear chips 105 and the interposers 106 are made common.
For the above conventional technique, the interposers 106 are essential for unifying the interconnection patterns from the external electrodes of the individual semiconductor bear chips. In the prior art, there was no technique to realize the multilevel structure of only the semiconductor bear chips without using the interposers for the purpose of unifying the interconnection patterns from the external electrodes of the individual semiconductor bear chips.
Further, the requirement for reduction in thickness of the semiconductor bear chips has been on the increase, whereby it has been necessary that a gap between adjacent two of the stacked semiconductor bear chips is as narrow as possible. This narrowed gap between adjacent two of the stacked semiconductor bear chips makes it difficult to conduct the required test for certain connections between the individual stacked semiconductor bear chips by use of a probe.
In the above circumstances, it had been required to develop a novel semiconductor device having an improved multilevel stacked structure free from the above problem.
Accordingly, it is an object of the present invention to provide a novel semiconductor device having an improved multilevel stacked structure free from the above problems.
It is a further object of the present invention to provide a novel semiconductor device having an improved multilevel stacked structure allowing unification of electrode patterns and interconnection layout throughout multilevel stacked semiconductor bear chips.
It is a still further object of the present invention to provide a novel semiconductor device having an improved multilevel stacked structure allowing efficient use of signal lines in stacking plural semiconductor bear chips.
It is yet a further object of the present invention to provide a novel semiconductor device having an improved multilevel stacked structure allowing a test for certain connections between multilevel stacked semiconductor bear chips.
The present invention provides a semiconductor device comprising a plurality of semiconductor bear chips staked over a substrate, each of the semiconductor bear chips having top and bottom surfaces, each of the top and bottom surfaces of each of the semiconductor bear chips having both plural signal pads and plural chip select pads, wherein the plural chip select pads are aligned at a constant pitch in a first direction, and adjacent two of the plural semiconductor bear chips are displaced by a first distance corresponds to the constant pitch in the first direction.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.